Plasma process induced damage (PPID) can be caused during front-end of the line (FEOL) or back-end of the line (BEOL) steps of the manufacturing process. This damage is caused by the accumulation of charges collected by floating conductors which act like antennas during a plasma processes. In response to this, manufacturers normally limit the size of large plates of metal or polysilicon connected to gate of a transistor by what is called “antenna rules”. The PPID problem is severe for thick oxide FETs, as thin oxide FETs have their gate oxide thickness in tunneling injection regime which allows the accumulated charge to tunnel from gate to the substrate. For the thick oxide devices, as the gate oxide thickness is large, there is not much leakage current through tunneling. This enables buildup of the charge at the gate electrode, raising its potential and finally breaking down the oxide or dielectric stack. In some cases, it could be a “hard” breakdown which render the device useless, while some other times it can create latent defects in the gate oxide stack which limits the lifetime of the device. The protection against this is done by limiting the antenna sizes and by requiring protection diodes. But the problem with protection diodes is that they can be connected only at or after laying the first metal level (M1). Lately, industry is employing more and more plasma rich processes in FEOL which cannot be protected by a gate tie-down diode after M1 (first metal). What is needed is a technique for protecting against PPID before M1.
The antenna effect, more formally plasma induced gate oxide damage, is an effect that can potentially cause yield and reliability problems during the manufacture of MOS integrated circuits. Fabs normally supply antenna rules, which are rules that must be obeyed to avoid this problem. A violation of such rules is called an antenna violation. The word antenna is somewhat of a misnomer in this context—the problem is really the collection of charge, not the normal meaning of antenna, which is a device for converting electromagnetic fields to/from electrical currents. Occasionally the phrase antenna effect is used this context, but this is less common since there are many effects and the phrase does not make clear which is meant.
The Field Effect Transistor
The transistor is a solid state semiconductor device which can be used for amplification, switching, voltage stabilization, signal modulation and many other functions. Generally, a transistor has four terminals, and a voltage applied to a specific one of the terminals controls current flowing between the other two terminals.
The terminals of a field effect transistor (FET) are commonly named source, gate, drain and substrate. In the FET a small amount of voltage is applied to the gate (G) in order to control current flowing between the source (S) and drain (D). In FETs the main current appears in a narrow conducting channel formed near (usually primarily under) the gate. This channel connects electrons from the source terminal to the drain terminal. The channel conductivity can be altered by varying the voltage applied to the gate terminal, enlarging or constricting the channel and thereby controlling the current flowing between the source and the drain.
FIGS. 1A and 1B illustrate an exemplary, conventional field effect transistor (FET) 100. FIG. 1A is a plan view, and FIG. 1B is a cross-sectional view taken on a line 1B-1B through FIG. 1A.
The FET 100 is formed upon a semiconductor substrate 102, and more particularly within a cell well (CW) portion of the substrate 102. The cell well (CW) is a region of the substrate 102 which has been doped, for example, to be an “n-well” within a “p-type” substrate.
The term “substrate” as used herein is intended to include a semiconductor substrate, a semiconductor epitaxial layer deposited or otherwise formed on a semiconductor substrate and/or any other type of semiconductor body, and all such structures are contemplated as falling within the scope of the present invention. For example, the semiconductor substrate may comprise a semiconductor wafer (e.g., silicon, Ge, III-V compounds like GaAs, SiGe, or an SOI wafer) or one or more die on a wafer, and any epitaxial layers or other type semiconductor layers formed there over or associated therewith.
While particular n- and p-type doping are described herein according to NMOS technology, it is to be appreciated that one or more aspects of the present invention are equally applicable to forming a PMOS (generally, simply by reversing the n- and p-type doping).
As best viewed in FIG. 1B, the FET 100 comprises a p-type substrate, and two spaced-apart n-type diffusion areas—one of which will serve as the “source”, the other of which will serve as the “drain” of the transistor. The space between the two diffusion areas is called the “channel”. The channel is where current flows, between the source (S) and the drain (D). A schematic symbol for an n-channel MOSFET appears to the left of FIG. 1B.
A thin dielectric layer is disposed over the substrate in the neighborhood of the channel, and a “gate” structure (G) is disposed over the dielectric layer atop the channel. (The dielectric under the gate is also commonly referred to as “gate oxide” or “gate dielectric”.) Electrical connections (not shown) may be made to the source (S), the drain (D), and the gate (G). The substrate may be grounded (connected to electrical “ground”).
Generally, when there is no voltage applied to the gate, there is no electrical conduction (connection) between the source and the drain. As voltage (of the correct polarity, plus or minus) is applied to the gate, there is a “field effect” in the channel between the source and the drain, and current can flow between the source and the drain. This current flowing in the channel can be controlled by the voltage applied to the gate. In this manner, a small signal (gate voltage) can control a relatively large signal (current flow between the source and the drain).
An integrated circuit (IC) device may comprise many millions of FETs on a single semiconductor “chip” (or “die”), measuring only a few centimeters on each side. Several chips may be formed simultaneously, on a single “wafer”, using conventional semiconductor fabrication processes including deposition, doping, photolithography, and etching. As best viewed in FIG. 1A, a trench, labeled “STI” surrounds a single FET 100. “STI” is short for silicon (or shallow) trench isolation, and generally involves forming (such as by etching into the surface of the substrate) a trench around the FET, and filling (such as by deposition) the trench with an insulating material such as silicon dioxide (commonly referred to simply as “oxide”). There can be more than one FET isolated in a STI area. But all of the FETs in a given STI area should be either NFET or PFET (of the same polarity), rather than mixed (both, having opposite polarities).
Although only one STI trench (and a corresponding one FET) is shown in FIG. 1A, it should be understood that the trench may be formed by several intersecting, parallel trenches (like a tic-tac-toe board), as indicated by the dashed lines. The STI insulates (electrically isolates) the enclosed FET from other, neighboring FETs. The area within the trench is referred to as the active silicon region, and may be referred to as “AA”. In modern day IC technology, STI is considered to be indispensable. STI is omitted from the view of FIG. 1B, for illustrative clarity.
Normally, the depth of the STI trench will be same across the wafer. But the width of the trench can be different across the wafer. The width of the trench (in the X or Y direction) can narrower than its depth, but it generally cannot be too narrow which is usually a process limitation for every technology node. A plurality of STI trenches (and corresponding plurality of FETs) can be located in the same (a common) cell well which usually extends lower than and underneath the STI trench.